An electronic integrated circuit chip conventionally comprises one or more electronic components formed in a semiconductor wafer before the semiconductor wafer is diced and, on one face, one or more contact metallizations (for example, pads) intended to be soldered to an external device outside the integrated circuit chip, for example a printed circuit board or another integrated circuit chip.
In certain applications, there is a need for integrated circuit chips that can be used directly without packaging, in particular diodes and more particularly protection diodes, in which the lateral faces, or flanks, of the integrated circuit chip are coated with an electrically insulating layer. Laterally insulating the integrated circuit chip in such a way makes it possible in particular to prevent, when the soldering is being carried out, the potential creep of solder up the flanks (sides) of the integrated circuit chip which may lead to a formation of a short circuit between the electrodes and the substrate of the integrated circuit chip.
FIG. 1 is a cross-sectional view of a diode 1 delimited by dotted lines and formed from the upper face of a semiconductor wafer 3, for example a silicon wafer. At this stage, the diode 1 is integral with the wafer 3.
The diode 1 is formed by an n-doped well 5 located within a p-doped region 7 of the semiconductor wafer 3. The well 5 is, for example, formed from and at the upper surface of the region 7.
Contact regions 9, 11 are formed in the well 5 and the region 7, respectively. The region 9 is n-doped and has an n+ level of doping that is higher than the doping level of the n-doped well. The region 11 is p-doped and has a p+ level of doping that is higher than the doping level of the region 7.
Cathode and anode contacts 13, 15 are formed on the contact regions 9, 11. The anode contact 15 is formed on the contact region 11 (on the right in FIG. 1). The cathode contact 13 is formed on the contact region 9 (on the left in FIG. 1). The contacts 13, 15 are made of a metal, of a superposition of metals, or of an alloy of various metals.
The upper face of this structure, apart from the contacts 13, 15, is covered with a passivation layer 17.
In practice, multiple diodes, or other electronic components, may be produced simultaneously from one and the same semiconductor wafer 3. For the sake of simplicity, only a single diode 1 is shown here.
FIG. 2 is a cross-sectional view of a step of a method for fabricating a laterally insulated integrated circuit chip 19. The integrated circuit chip 19 is an integrated circuit chip intended for use without a package. By way of example, the integrated circuit chip 19 comprises a diode that is identical to the diode 1 described with reference to FIG. 1.
In this step, a trench 23 entirely surrounding (when seen from above, encircling) the integrated circuit chip 19 is etched. The trench 23 defines the lateral faces of the integrated circuit chip 19. The trench 23 extends into the wafer 3 to a depth that is greater than or equal to the desired thickness of the integrated circuit chip 19. The trench 23 is not a through-trench, i.e. it does not extend all the way to the lower surface of the wafer 3.
Conventionally, the trench 23 is produced by means of a deep reactive ion etching process or by means of an etching process known as the Bosch process (a process of this type is described in U.S. Pat. No. 5,501,893, incorporated by reference). Such a process leads to the formation of a layer of polymer on the walls of the trench 23. This layer of polymer is generally regarded as a contaminant. Thus, the etching process is followed by a step of chemical cleaning to remove the layer of polymer.
Next, an insulating layer, for example a layer of silicon dioxide, is deposited conformally in the trench 23 in order to insulate the walls of the trench which form, as mentioned above, the lateral walls of the integrated circuit chip 19. The semiconductor wafer 3 is then cut via its back face in order to singulate the integrated circuit chip 19 by separating it from the wafer 3.
There is a need in the art for an improved method for fabricating a laterally insulated integrated circuit chip that minimizing the needed number of processing steps.